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rbic lite tm analog output sensor signal conditioner zsc31010 datasheet ? 2016 integrated device technology, inc. 1 january 20, 2016 zsc31010 bsink vbp vbn vss sig? vgate 0.1f v supply ground +4.5 to +5.5 v out/owi vdd 10nf brief description the zsc31010 is a sensor signal con ditioner inte - grated circuit, which enables easy and precise calibration of resistive bridge sensors via eeprom. when mated to a resistive bridge sensor, it will digitally correct offset and gain with t he option to correct offset and gain coefficients and linearity over temperature. a second - order compensation can be enabled for temperature coefficients of gain or offset or bridge linearity. the zsc31010 communi cates via idt ?s zacwire? serial interfa ce to the host computer and is easily mass calibrated in a windows? environment. once calibrated, the output pin sig? can provide selectable 0 to 1 v, rail - to - rail ratiometric analog output, or digital serial output of bridge data with optional temperature data. features ? digital compensation of sensor offset, sensitivity, temperature drift, and non - linearity ? accommodates differential sensor signal spans, from 3 mv/v to 105 mv/v ? zacwire? one - wire interface (owi) ? internal temperature compensation and detectio n via bandgap ptat (proportional to absolute temperature) ? output options: rail - to - rail analog output voltage, absolute analog voltage, digital zacwire? one - wire interface (owi) ? optional sequential output of both temperature and bridge readings on zacwire? digital output ? fast response time, 1 ms (typical) ? high voltage protection up to 30 v with external jfet ? chopper - stabilized true differential adc ? buffered and chopper - stabilized output dac benefits ? no external trimming components required ? simple pc - contro lled configuration and calibration via zacwire? one - wire interface ? high accuracy (0.1% fso @ - 25 to 85c; 0.25% fso @ - 50 to 150c) ? single pass calibration ? quick and precise ? suitable for battery - powered applications ? small sop8 package available support ? development kit available ? mass calibration kit available ? support for industrial mass calibration available ? quick circuit customization possible for large production volumes physical characteristics ? supply voltage 2.7 to 5.5 v, with external jfet 5.5v to 3 0 v ? current consumption depending on adjusted sample rate: 0.25 ma to 1 ma ? wide operational temperature: ? 50 to +150c zsc31010 application circuit ? digital output
rbic lite tm analog output sensor signal conditioner zsc31010 datasheet ? 2016 integrated device technology, inc. 2 january 20, 2016 2 1 5 6 7 8 3 4 zsc 31010 bsink vbp n / c vbn vss s ig tm vdd vgate 0 . 1 m f v supply ground + 5 . 5 to + 30 v out optional bsink s d jfet 10 n f adc analog block digital block rbic lite ? zsc 31010 0 v to 1 v ratiometric rail - to - rail owi / zacwire tm 0 . 1 m f vss vbp dac outbuf zacwire tm interface dsp eeprom preamp inmux temp . reference vdd regulator power save por osc . vbn vgate vdd sig tm bsink optional 2 . 7 to 5 . 5 v jfet ( optional if supply is 2 . 7 to 5 . 5 v ) d s v supply 5 . 5 v to 30 v 1 n f highly versatile applications in man y markets including ? industrial ? building automation ? office automation ? white goods ? automotive ? portable devices ? your innovative designs 2 1 5 6 7 8 3 4 zsc31010 bsink vbp n/c vbn vss sig tm vdd vgate 0.1 mf v supply ground +2.7 to + 5.5 v out optional bsink 10 nf zsc31010 block diagram rail -to - rail ratiometric voltage output applications abso lute analog voltage output applications ordering examples (please see section 11 in the data sheet for additional options.) sales code description package zsc31010 ceb zsc31010 die ? temperature range: - 50c to +150c unsawn on wafer zsc31010 cec zsc31010 die ? temperature range: - 50c to +150c sawn on wafer frame zsc31010 ceg1 zsc31010 sop8 (150 mil) ? temperature range: - 50c to +150c tube: add ? - t? to sales code reel: add ? - r? zsc31010 kit zsc31010 zacwi re? ssc evaluation kit: communication board, ssc board, sensor replacement board, usb cable, 5 ic samples kit corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com sales 1- 800- 345- 701 5 or 408- 284- 8200 fax: 408 - 284- 2775 www.idt.com/go/sales tech support www.idt.com/go/support disclaimer integrated device technology, inc. (idt) reserves the rig ht to modify the products and/or specifications described herein at any time, without notice, at idt's sole discretion. perfo rmance specifications and operating parameters of the described products are determined in an independent state and are not guarant eed to perform the same way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, includin g, but not limited to, the suitability of idt's products for a ny particular purpose, an implied warranty of merchantability, or non - infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey an y license under intellectual property rights of idt or any th ird parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly af fect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express , written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the united states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . all contents of this document are copyright of integrated device technology, inc. all rights reserved.
zsc31010 datasheet ? 2016 integrated device technology, inc. 3 january 20, 2016 contents list of figures ............................................................................................................................................................. 4 list of tables .............................................................................................................................................................. 5 1 electrical characteristics ..................................................................................................................................... 6 1.1. absolute maximum ratings .......................................................................................................................... 6 1.2. recommended operating conditions .......................................................................................................... 6 1.3. electrical parameters ................................................................................................................................... 7 1.3.1. supply/ regulation characteristics ......................................................................................................... 7 1.3.2. analog front - end (afe) characteristics ................................................................................................ 7 1.3.3. eeprom parameters ............................................................................................................................ 7 1.3.4. a/d converter characteristics ............................................................................................................... 7 1.3.5. analog output (dac and buffer) characteristics .................................................................................. 7 1.3.6. zacwire? serial interface .................................................................................................................... 8 1.3.7. system response characteristics ......................................................................................................... 8 1.4. analog inputs versus output resolution ...................................................................................................... 9 2 circuit description ............................................................................................................................................. 11 2.1. signal flow and block diagram .................................................................................................................. 11 2.2. analo g front end ........................................................................................................................................ 12 2.2.1. bandgap/ptat and ptat amplifier .................................................................................................... 12 2.2.2. bridge supply ....................................................................................................................................... 12 2.2.3. preamp block .................................................................................................................................... 12 2.2.4. analog - to - digital converter (adc) ....................................................................................................... 12 2.3. digital signal processor ............................................................................................................................. 13 2.3.1. eeprom .............................................................................................................................................. 14 2.3.2. one - wire interface ? zacwire? .......................................................................................................... 14 2.4. output stage ............................................................................................................................................... 15 2.4.1. digital to analog converter (output dac) ........................................................................................... 15 2.4.2. output buffer ........................................................................................................................................ 15 2.4.3. voltage reference block ..................................................................................................................... 15 2.5. clock generator / power - on reset (clkpor) ......................................................................................... 16 2.5.1. trimming the oscillator ........................................................................................................................ 17 3 functional description ....................................................................................................................................... 18 3.1. general working mode ............................................................................................................................... 18 3.2. zacwire? communi cation interface ......................................................................................................... 19 3.2.1. properties and parameters .................................................................................................................. 19 3.2.2. bit encoding ......................................................................................................................................... 20 3.2.3. write operation from master to zsc31010 ......................................................................................... 20 3.2.4. zsc31010 read operations ................................................................................................................ 21 3.2.5. high level protocol .............................................................................................................................. 24
zsc31010 datasheet ? 2016 integrated device technology, inc. 4 january 20, 2016 3.3. command/data bytes encoding ................................................................................................................ 24 3.4. calibration sequence ................................................................................................................................. 25 3.5. eeprom bits ............................................................................................................................................. 27 3.6. calibration math ......................................................................................................................................... 29 3.6.1. correction coefficients ......................................................................................................................... 29 3.6.2. interpretation of binary numbers for correction coefficients .............................................................. 30 3.7. reading eeprom contents ...................................................................................................................... 34 4 application circu it examples ............................................................................................................................. 35 4.1. three - wire rail - to - rail ratiometric output ................................................................................................ 35 4.2. absolute analog voltage output ................................................................................................................ 36 4.3. three - wire ratiometric output with over - voltage protection ................................................................... 36 4.4. digital output .............................................................................................................................................. 37 4. 5. output short protection .............................................................................................................................. 37 5 default eeprom settings ................................................................................................................................ 38 6 pin configuration and package ......................................................................................................................... 39 7 esd/latch - up - protection .................................................................................................................................. 40 8 test .................................................................................................................................................................... 40 9 quality and reliability ........................................................................................................................................ 40 10 customization .................................................................................................................................................... 40 11 ordering codes ................................................................................................................................................. 41 12 related documents ........................................................................................................................................... 41 13 definitions of acronyms ..................................................................................................................................... 41 14 document revision history ............................................................................................................................... 42 list of figures figure 2.1 zsc31010 block diagram ................................................................................................................... 11 figure 2.2 dac output timing for highest update rate ...................................................................................... 15 figure 3.1 general working mode ........................................................................................................................ 18 figure 3.2 manchester duty cycle ........................................................................................................................ 20 figure 3.3 19- bit write frame ............................................................................................................................... 20 figure 3.4 read acknowledge .............................................................................................................................. 21 figure 3.5 digital output (nom) bridge readings ............................................................................................... 21 figure 3.6 digital output (nom) bridge readings with temperature .................................................................. 22 figure 3.7 read eeprom contents .................................................................................................................... 22 figure 3.8 transmission of a number of data packets ........................................................................................ 22 figure 3.9 zacwire? output timing for lower update rates ............................................................................. 23 figure 4.1 rail - to - rail ratiometric voltage output ............................................................................................... 35
zsc31010 datasheet ? 2016 integrated device technology, inc. 5 january 20, 2016 figure 4.2 absolute analog voltage output .......................................................................................................... 36 figure 4.3 ratiometric output, temperature compensation via internal diode ................................................... 36 figure 6.1 zsc31010 pin - out diagram ................................................................................................................ 39 list of tables table 1.1 adc resolution characteristics for an analog gain of 6 ...................................................................... 9 table 1.2 adc resolution characteristics for an analog gain of 12 .................................................................... 9 table 1.3 adc resolution characteristics for an analog gain of 24 .................................................................. 10 table 1.4 adc resolution characteristics for an analog gain of 48 .................................................................. 10 table 2.1 order of trim codes ............................................................................................................................ 16 table 2.2 oscillator trimming .............................................................................................................................. 17 table 3.1 pin configuration and latch - up conditions ........................................................................................ 19 table 3.2 total transmissi on time for different update rate settings and output configuration ..................... 23 table 3.3 special measurement versus update rate ......................................................................................... 23 table 3 .4 command/data bytes encoding .......................................................................................................... 24 table 3.5 programming details for command 30 h .............................................................................................. 25 table 3.6 zsc31010 eeprom bits .................................................................................................................... 27 table 3.7 correction coefficients ........................................................................................................................ 29 table 3.8 gain_b[13:0] weightings ..................................................................................................................... 30 table 3.9 offset_b weightings ............................................................................................................................ 31 table 3.10 gain_t weightings .............................................................................................................................. 31 table 3.11 offset_t weightings ............................................................................................................................ 32 table 3.12 eeprom read order ......................................................................................................................... 34 table 4.1 resistor values for short protection ................................................................................................... 37 table 5.1 factory sett ings for the zsc31010 eeprom ..................................................................................... 38 table 6.1 storage and soldering conditions for the sop - 8 package ................................................................. 39 table 6.2 zsc31010 pin configu ration ............................................................................................................... 39
zsc31010 datasheet ? 2016 integrated device technology, inc. 6 january 20, 2016 1 electrical characteristics 1.1. absolute maximum ratings note: the absolute maximum ratings are stress ratings only. the device might not function or be operable above the operating conditions given in section 1.2 . stresses exceeding the absolute maximum ratings might also damage the device . in addition, extended exposure to stresses above the recommended operating conditions might affect device reliability. idt does not recommend designing to the ?absolute maximum ratings.? parameter symbol conditions min max unit analog supply voltage v dd - 0.3 6.0 v voltages at analog i/o ? in pin v ina - 0.3 vdd+0.3 v voltages at analog i/o ? out pin v outa - 0.3 vdd+0.3 v storage te mperature range t stg -50 150 c storage temperature range t stg <10h for periods < 10 hours -50 170 c note: also see table 6.1 regarding soldering temperature and storage conditions for the sop -8 package. 1.2. recom mended operating conditions parameter symbol conditions min typ max unit analog supply voltage to ground v dd 2.7 5.0 5.5 v analog supply voltage (with external jfet regulator) v supp 5.5 7 30 v common mode voltage v cm 1 v dda - 1.3 v ambient tempera ture range 1, 2) t amb -50 150 c external capacitance between v dd and ground c vdd 100 220 470 nf output load resistance to v dd r l,out 2.5 10 k ? output load resistance to v ss 3) 4) r l,out 2. 5 20 k ? output load capacitance 5 ) c l,out 1 10 15 nf b ridge resistance 6 ) r br 0.2 100 k ? power on rise time t pon 100 ms 1) note that the maximum eeprom programming temperature is 85c. 2) if buying die, designers should use caution not to exceed maximum junction temperature by proper package selection. 3) when using the output for digital calibration, no pull down resistor is allowed. 4) for loads less than 20 k ? to vss an equivalent strength (or lower ) pull - up resistor must be added . 5) using the output for digital calibration, c l,out is limited by the maximum rise t ime t zac,rise . 6) note: minimum bridge resistance is only a factor if using the bsink feature. the nominal r ds (on) of the bsink transistor is 10 when operating at v dd = 5 v, and 15 when operating at v dd = 3.0 v. this does give rise to a ratiometricity inaccuracy that becomes greater with low bridge resistances.
zsc31010 datasheet ? 2016 integrated device technology, inc. 7 january 20, 2016 1.3. electrical parameters see important table notes at the end of the table. note: for parameters marked with an asterisk, there is no verification in mass production; the parameter is guaranteed by design and/or quality observation . parameter symbol conditions min typ max unit 1.3.1. supply/regulation characteri stics supply voltage v dd 2.7 5.0 5.5 v supply current (varies with update rate and output mode) i dd at minimum update rate 0.25 m a at maximum update rate 1.0 1.2 temperature coefficient ? regulator (worst case) * tc reg tem. - 10c to 120c 35 ppm/k temp. < - 10c and > 120c 100 power supply rejection ratio * psrr dc < 100 hz (jfet regulation loop using mmbf4392 and 0.1 f decoupling cap) 60 db ac < 100 khz (jfet regulation loop using mmbf4392 and 0.1 m f decoupling cap) 45 db pow er - on reset level por 1.4 2.6 v 1.3.2. analog front - end (afe) characteristics leakage current pin vbp,vbn i in_leak 10 na 1.3.3. eeprom parameters number write cycles n wri_eep at 150 c at 85 c 100 100k cycles data retention t wri_eep at 100 c 10 years 1.3.4. a/ d converter characteristics adc resolution r adc 14 bit integral nonlinearity (inl) 1) inl adc -4 +4 lsb differential nonlinearity (dnl) * dnl adc -1 +1 lsb response time t res,adc varies with update rate . value given at fastest rate. 1 ms 1.3.5. analog output (dac and buffer) characteristics max. output current i out max. current maintaining accuracy 2.2 ma resolution r out referenced to v dd 11 bit absolute error e abs dac input to output -10 +10 mv dif ferential nonlinearity * dnl no missing codes - 0.9 +1.5 lsb 11bit upper output voltage limit v out r l = 2.5 k ? 95% v dd lower output voltage limit v out 16.5 mv
zsc31010 datasheet ? 2016 integrated device technology, inc. 8 january 20, 2016 parameter symbol conditions min typ max unit 1.3.6. zacwire? serial interface zacwire ? line resistance * r zac,line the rise time t zac,rise mu st be 2 ? r zac,line ? c zacload 5 s. if using a pull - up resistor instead of a line resistor, it must meet this specification. 3.9 k ? zacwire ? load capacitance * c zac,load 0 1 15 nf zacwire ? rise time * t zac,rise 5 s voltage level low * v zac,low 0 0.2 v dd voltage level high * v zac,low 0.8 1 v dd 1.3.7. system response characteristics start -up - time t sta power - up to output 10 ms response time t resp update_rate = 1 khz (1 ms) 1 2 ms sampling rate f s update_rate = 1 khz (1 ms) 1000 hz overall linearity error e lind bridge input to output ? digital 0.025 0.04 % overall linearity error e lina bridge input to output ? analog 0.1 0.2 % overall ratiometricity error re out 10%vdd, n ot using bsink feature 0.035 % overall accuracy ? digital (only ic, without sensor bridge) ac outd - 25c to 85c 0.1% %fso - 50c to 150c 0.25% overall accuracy ? analog (only ic, withou t sensor bridge) 2) , 3) ac outa - 25c to 85c 0.25% %fso - 40c to 125c 0.35% - 50c to 150c 0.5% 1) note: this is 4 lsbs to the 14 - bit a - to - d convers ion. this implies absolute accuracy to 12 bits on the a - to - d result. non - linearity is typically better at temperatures less than 125 c. 2) not included is the quantization noise of the dac. the 11 - bit dac has a quantization noise of ? lsb = 1.22 mv (5v vd d) = 0.025% 3) analog output range 2.5% to 95%.
zsc31010 datasheet ? 2016 integrated device technology, inc. 9 january 20, 2016 1.4. analog inputs versus output resolution the zsc31010 incorporates an extended 14 - bit charge - balanced adc, which allows for a single gain setting on the pre - amplifier to handle bridge sensitivities from 1.2 to 36 mv/v while maintaining 8 to 12 bits of output reso - lution with a default analog gain of 24 . selectable gain settings allow accommodating bridges with different sensitivities. the tables below illustrate the minimum resolution achievable for a variety of bridge sensitivities. the yellow shadowed fields indicate that for these input spans with the selected analog gain setting, the quantization noise is higher than 0.1% fso. table 1 . 1 adc resolution characteris tics for an analog gain of 6 analog gain 6 input span [mv/v] allowed offset (+/ - % of span) 1) minimum guaranteed resolution [bits] min typ max 57.3 80.0 105.8 38% 13.3 50.6 70.0 92.6 53% 13.1 43.4 60.0 7 9.4 73% 12.9 36.1 50.0 66.1 101% 12.6 28.9 40.0 52.9 142% 12.3 21.7 30.0 39.7 212% 11.9 1) in addition to tco, tcg table 1 . 2 adc resolution characteristics for an analog gain of 12 analog gain 12 input span [mv/v] allowed offset (+/ - % of span) 1) minimum guaranteed resolution [bits] min typ max 43.3 60.0 79.3 3% 13.0 36.1 50.0 66.1 17% 12.7 25.3 35.0 46.3 53% 12.2 18.0 25.0 33.0 101% 11.7 14.5 20.0 26.45 142% 11.4 7.2 10.0 13.22 351% 10.4 3.6 5.0 6.6 767% 9.4 1) in addition to tco, tcg note: yellow shadowing indicates that for these input spans with the selected analog gain setting, the quantization noise is > 0.1% fso.
zsc31010 datasheet ? 2016 integrated device technology, inc. 10 january 20, 2016 table 1 . 3 adc resolution characteristics for an analog gain of 24 analog gain 24 input span [mv/v] allowed offset (+/ - % of span) 1) minimum guaranteed resolution [bits] min typ max 16 25.0 36 25% 12.6 12.8 20.0 28.8 50% 12 6.4 10.0 14. 4 150% 11 3.2 5.0 7.2 400% 10 1.6 2.5 3.6 900% 9 0.8 1.2 1.7 2000% 8 1) in addition to tco,tcg note: yellow shadowing indicates that for these input spans with the selected analog gain setting, the quantization noise is > 0.1% fso. table 1 . 4 adc resolution characteristics for an analog gain of 48 analog gain 48 input span [mv/v] allowed offset (+/ - % of span) 1) minimum guaranteed resolution [bits] min typ max 10.8 15.0 19.8 3% 13 7.2 10.0 13.2 35% 12. 4 4.3 6.0 7.9 100% 11.7 2.9 4.0 5.3 190% 11.1 1.8 2.5 3.3 350% 10.4 1.0 1.4 1.85 675% 9.6 0.72 1.0 1.32 975% 9.1 1) in addition to tco,tcg note: yellow shadowing indicates that for these input spans with the selected analog gain setting, the quantizatio n noise is > 0.1% fso.
zsc31010 datasheet ? 2016 integrated device technology, inc. 11 january 20, 2016 2 circuit description 2.1. signal flow and block diagram the zsc31010 resistive bridge sensor interface ics were specifically designed as a cost - effective solution for sensing in building automation, industrial, office automation, and whi te goods applications. the rbic lite ? employs idt ?s high precision bandgap with proportional - to - absolute temperature (ptat) output; a low - power 14 - bit analog - to - digital converter (adc, a2d, a - to - d); and an on - chip dsp core with eeprom to precisely calib rate the bridge output signal. three selectable output modes, two analog and one digital, offer the ultimate in versatility across many applications. the zsc31010 rail - to - rail ratiometric analog output vout signal (0 to 5 v, vout @ vdd = 5 v) suits most bu ilding automation and automotive requirements. typical office automation and white goods applications require the 0 to 1 vout signal, which in the zsc31010 is referenced to the internal bandgap. direct interfacing to microprocessor controllers is facilitat ed via idt ?s single - wire serial zacwire? digital interface. the zsc31010 is capable of running in high - voltage (5.5 to 30 v) systems when combined with an external jfet. figure 2 . 1 zsc31010 block diagram adc analog block digital block rbic lite ? zsc31010 0 v to 1 v ratiometric rail-to-rail owi/ zacwire tm 0.1 mf vss vbp dac outbuf zacwire tm interface dsp eeprom preamp inmux temp. reference vdd regulator power save por osc. vbn vgate vdd sig tm bsink optional 2.7 to 5.5 v jfet (optional if supply is 2.7 to 5.5 v) d s v supply 5.5 v to 30 v 1nf
zsc31010 datasheet ? 2016 integrated device technology, inc. 12 january 20, 2016 2.2. analog front end 2.2.1. bandgap/ptat and ptat amplifier the highly linear bandgap/ptat provides the ptat signal to the adc, which allows accurate temperature con - version. in addition, the ultra - low ppm - bandgap provides a stable volt age reference over temperature for the operation of the rest of the ic. the ptat signal is amplified through a path in the pre - amplifier (preamp) and fed to the adc for conversion. the most significant 12 bits of this converted result are used for temperat ure measurement and temperature correction of bridge readings. when temperature is output in digital mode, only the most significant 8 bits are given. 2.2.2. bridge supply the voltage driven bridge is usually connected to v dd and ground. as a power savings featur e, the zsc31010 also includes a switched transistor to interrupt the bridge current via the bsink pin. the transistor switching is synchronized to the a/d - conversion and released after finishing the conversion. to utilize this feature, the low supply of th e bridge should be connected to bsink instead of ground. depending on the programmable update rate, the average current consumption (including bridge current) can be reduced to approximately 20%, 5% or 1%. 2.2.3. preamp block the differential signal from the brid ge is amplified through a chopper - stabilized instrumentation amplifier with very high input impedance, designed for low noise and low drift. this preamp provides gain for the differential signal and re - centers its dc to v dd /2. the output of the preamp bloc k is fed into the a/d - converter. the calibration sequence performed by the digital core includes an auto - zero sequence to null any drift in the preamp state over temperature. the preamp is nominally set to a gain of 24. other possible gain settings are 6, 12, and 48. the inputs to the preamp from the vbn/vbp pins can be reversed via an eeprom configuration bit. 2.2.4. analog - to - digital converter (adc) a 14 - bit/1 ms 2 nd - order charge - balancing adc is used to convert signals coming from the preamp. the con - verter, de signed in full differential switched - capacitor technique, is used for converting the various signals to the digital domain. this principle offers the following advantages: ? high noise immunity because of the differential signal path and integrating behavior ? independent from clock frequency drift and clock jitter ? fast conversion time owing to second order mode four selectable values for the zero point of the input voltage allow the conversion to adapt to the sensor?s offset parameter. the conversion rate vari es with the programmed update rate. the fastest conversion rate is 1 k samples/s; the response time is then 1 ms. based on a best fit, the integral nonlinearity (inl) is < 4 lsb 14bit .
zsc31010 datasheet ? 2016 integrated device technology, inc. 13 january 20, 2016 ) tco t b _ offset raw _ br ( ) tcg t 1 ( b _ gain zb ? ? + + ? ? ? + = ) zb sot 25 . 1 ( zb br ? + = 2.3. digital signal processor a digital signal processor (dsp) is used for pr ocessing the converted bridge data as well as for performing temperature correction and for computing the temperature value for output on the digital channel. the dsp reads correction coefficients from the eeprom and can correct for ? bridge offset ? bridge ga in ? variation of bridge offset over temperature (tco) ? variation of bridge gain over temperature (tcg) ? a single second order effect (sot - second order term) the eeprom contains a single sot that can be applied to correct one and only one of the following: ? 2 nd order behavior of bridge measurement ? 2 nd order behavior of tco ? 2 nd order behavior of tcg (for more details, see section 3.6.1 .) if the sot applies to correcting the bridge reading, then the correction formul a for the bridge reading is re presented as a two step process as follows: (1) (2) ` where: br = corrected bridge reading that is fed as digital or analog output on sig? pin zb = intermediate result in the calculations br_raw = raw bridge reading from adc t_raw = raw temperature reading converted from ptat signal gain_b = bridge gain term offset_b = bridge offset term tcg = temperature coefficient gain tco = temperature coefficient offset ? t = ( t_raw - t setl ) t_raw = raw temperature reading converted from ptat signal t setl = raw ptat reference value (see technical note ? zsc31010, zsc31015, and zssc3015 calibration sequence, dll, and exe for details. ) sot = second order term note: see section 3.6.2.7 for limitations when sot applies to the bridge reading.
zsc31010 datasheet ? 2016 integrated device technology, inc. 14 january 20, 2016 )] tco t sot ( t b _ offset raw _ br [ ) tcg t 1 ( b _ gain br + ? ? ? + + ? ? ? + = ] tco t b _ offset raw _ br [ )] tcg t sot ( t 1 [ b _ gain br ? ? + + ? + ? ? ? + = ) t _ offset raw _ t ( t _ gain t + = if the sot applies to correcting the 2 nd order behavior of tco , then the formula for bridge correction is as follows: (3) note: see section 3.6.2.7 for limitations when sot applies to tco. if the sot applies to correcting the 2 nd order behavior of tcg, then the formula for bridge correction is as follows: (4) the bandgap reference gives a very linear ptat si gnal, so temperature correction can always simply be accomplished with a linear gain and offset term. corrected temp reading: (5) where: t_raw = raw temperature reading converted from ptat signal offset_t = temperature sensor offset coefficient gain_t = te mperature gain coefficient 2.3.1. eeprom the eeprom contains the calibration coefficients for gain and offset, etc., and the configuration bits, such as output mode, update rate, etc. when programming the eeprom, an internal charge - pump voltage is used, so a high voltage supply is not needed. the eeprom is implemented as a shift register. during an eeprom read, the contents are shifted 8 bits before each transmission of one byte occurs. the charge - pump is internally regulated to 12.5 v, and the programming time is typically 6 ms. note: eeprom writing can only be performed at temperatures lower than 85 c . 2.3.2. one - wire interface ? zacwire? the ic communicates via a one - wire serial interface (owi, zacwire?). there are different commands available for the following: ? reading the conversion result of the adc (get_br_raw, get_t_raw) ? calibration commands ? reading from the eeprom (dump of entire contents) ? writing to the eeprom (trim setting, configuration, and coefficients)
zsc31010 datasheet ? 2016 integrated device technology, inc. 15 january 20, 2016 settling time 64 m s ad conversion 768 m s calculation 160 m s dac output occurs here dac output next update settling time 64 m s ad conversion 768 m s calculation 160 m s 2.4. output stage 2.4.1. digital to analog converter (output dac) an 1 1 - bit dac, based on sub - ranging resistor strings, is used for the digital - to - analog output conversion in the analog ratiometric and absolute analog voltage modes. selection during calibration configures the system to operate in either of these modes. the d esign allows for excellent testability as well as low power consumption. figure 2 . 2 shows the data timing of the dac output with the 1 khz update rate setting. figure 2 . 2 dac output timing for highest update rate 2.4.2. output buffer a rail - to - rail operational amplifier (opamp) configured as a unity gain buffer can drive resistive loads (whether pull - up or pull - down) as low as 2.5 k ? and capacitances up to 15 nf. to limit the error due to amplifier offset voltage, an error compensation circuit is included which tracks and reduces the offset voltage to < 1 mv. 2.4.3. voltage reference block a linear regulator control circuit is included in t he voltage reference block to interface with an external jfet to allow operation in systems where the supply voltage exceeds 5.5 v. this circuit can also be used for over - voltage protection. the regulator set point has a coarse adjustment via an eeprom bit (see section 2.3.1 ), which can adjust the set point around 5.0 v or 5.5 v. in addition, the 1 v trim setting (see below) can also act as a fine adjustment for the regulation set point. note: if using the extern al jfet for over - voltage protection purposes (i.e., 5 v at jfet drain and expecting 5 v at jfet source), there will be a voltage drop across the jfet; therefore ratiometricity will be compromised somewhat depending on the rds(on) of the chosen jfet. a vish ay j107 is the best choice, because it has only an 8 mv drop worst case. if using as regulation instead of over - voltage, an mmbf4392 also works well. the voltage reference block uses the absolute reference voltage provided by the bandgap to produce two reg ulated on - chip voltage references. a 1 v reference is used for the output dac high reference, when the part is configured for 0 to 1 v analog output. for this reason, the 1 v reference must be very accurate and includes trim, such that its value can be tri mmed within +/ - 3 mv of 1.0 v. the 1 v reference is also used as the on - chip reference for the jfet regulator block, so the regulation set point of the jfet regulator can be fine - tuned, using the 1 v trim. the 5 v reference can be trimmed within +/ - 15 mv. table 2 . 1 shows the order of trim codes with 0111 b for the lowest reference voltage, and 1000 b for the highest reference voltage.
zsc31010 datasheet ? 2016 integrated device technology, inc. 16 january 20, 2016 table 2 . 1 order of trim codes order 1v ref/5vref__trim3 1vref/5vref_trim2 1vref/5vref_trim1 1vref/5vref_trim0 highest reference voltage 1 0 0 0 ... 1 0 0 1 ... 1 0 1 0 ... 1 0 1 1 ... 1 1 0 0 ... 1 1 0 1 ... 1 1 1 0 ... 1 1 1 1 ... 0 0 0 0 ... 0 0 0 1 ... 0 0 1 0 ... 0 0 1 1 ... 0 1 0 0 ... 0 1 0 1 ... 0 1 1 0 lowest reference voltage 0 1 1 1 2.5. clock generator / power - on reset (clkpor) if the power supply exceeds 2.5 v (maximum), the reset signal de - asserts, and the clock generator starts oper - ating at a frequency of approximatel y 512 khz (+17% / - 22%). the exact value only influences the conversion cycle time and the communication to the outside world, but not the accuracy of signal processing. in addition, to minimize the oscillator error as the v dd voltage changes, an on - chip r egulator is used to supply the oscillator block.
zsc31010 datasheet ? 2016 integrated device technology, inc. 17 january 20, 2016 2.5.1. trimming the oscillator trimming is performed at wafer level, and it is strongly recommended that this is not to be changed during calibration, because zacwire? communication is no longer guaranteed at diffe rent oscillator frequencies. table 2 . 2 oscillator trimming trimming bits delta frequency (khz) 100 +385 101 +235 110 +140 111 +65 000 nominal 001 -40 010 -76 011 -110 example: programming 011 b the t rimmed frequency = nominal value - 110 khz.
zsc31010 datasheet ? 2016 integrated device technology, inc. 18 january 20, 2016 normal operation mode start_nom power on command mode raw mode no commands possible; measurement cycle; conditioning calculation (corrected bridge and temperature values) depending on the configuration, the sig tm pin is ? 0 v to 1 v; ? rail-to-rail ratiometric; or ? digital output measurement cycle stopped; full command set command routine will be processed after each command measurement cycle sig tm pin provides raw bridge and temperature values in this format: ? bridge_high (1 st byte) ? bridge_low (2 nd byte) ? temp (3 rd byte) start_rm command window (6 ms); send start_cm start_cm no command power off 3 functional description 3.1. general working mode the command/data transfer takes place via the one - wire sig? pin, using the zacwire? serial communi cation protocol. after power - on, the ic waits for 6 ms (i.e., the com mand window) for the start_cm command. without this command, the normal operation mode (nom) starts. in this mode, raw bridge values are converted, and the corrected values are presented on the output in analog or digital format (depending on the configura tion stored in eeprom). command mode (cm) can only be entered during the 6 ms command window after power - on. if the ic receives the start_cm command during the command window, it remains in the command mode. the cm allows changing to one of the other modes via command. after command start_rm, the ic is in the raw mode (rm). without correction, the raw values are transmitted to the digital output in a predefined order. the rm can only be stopped by power - off. raw mode is used by the calibration software for collection of raw bridge and temperature data, so the correction coefficients can be calculated. figure 3 . 1 general working mode
zsc31010 datasheet ? 2016 integrated device technology, inc. 19 january 20, 2016 3.2. zacwire? communication interface 3.2.1. properties and parameters table 3 . 1 pin configuration and latch - up conditions no. parameter symbol min typ max unit comments 1 pull - up resistor (on - chip) r zac,pu 30 k ? on - chip pull - up resistor switched on during digital output mode and during cm mode (first 6 ms after power up) 2 pull - up resistor (external) r zac,pu_ext 150 ? if the master communicates via a push - pull stage, no pull - up resistor is needed; otherwise, a pull - up resistor with a value of at least 150 ? must be connected. 3 zacwire? rise time t zac ,rise 5 s any user rc network included in sig? path must meet this rise time 4 zacwire? line resistance 1) r zac,line 3.9 k ? al so see section 1.3.6 in the specification tables. 5 zacwire? load capacitance 1) c zac ,load 0 1 15 nf also see section 1.3.6 in the specifi cation tables. 6 voltage low level v zac ,low 0 0.2 v dd rail -to - rail cmos driver 7 voltage high level v zac ,high 0.8 1 v dd rail -to - rail cmos driver 1) the rise time must be t zac,rise = 2 ? r zac,line ? c zacload 5 m s . if using a pull - up resistor instead o f a line resistor, it must meet this specification.
zsc31010 datasheet ? 2016 integrated device technology, inc. 20 january 20, 2016 bit window 106.8 sec @ 9.4khz baud 40sec @ 25khz baud start bit logic 1 logic 0 p 5 4 3 2 1 0 s command byte data byte s p 2 start bit parity bit of command or data byte command bit ( example : bit 2 ) 7 6 p 5 4 3 2 1 0 7 6 2 data bit ( example : bit 2 ) 19 - bit frame ( write ) 3.2.2. bit encoding figure 3 . 2 manchester duty cycle start bit = 50% duty cycle used to set up strobe time logic 1 = 75% duty cycle logic 0 = 25% duty cycle stop time the zacwire? bus will be held high for 32 s (nominal) between consecutive data packets regardless of baud rate. 3.2.3. write operation from master to zsc31010 the calibration master sends a 19 - bit packet frame to the zsc31010 . figure 3 . 3 19- bit write fram e the incoming serial signal will be sampled at a 512 khz clock rate. this protocol is very tolerant to clock skew and can easily tolerate baud rates in the 6 khz to 48 khz range.
zsc31010 datasheet ? 2016 integrated device technology, inc. 21 january 20, 2016 s data byte s p start bit parity bit of data byte data bit ( low ) p 1 0 0 1 0 1 1 0 1 data bit ( high ) 1 data byte packet ( 10 - bit byte a 5 h ) 0 3.2.4. zsc31010 read operations the incoming frame will be checked for proper pa rity on both, command and data bytes, as well as for any edge time - outs prior to a full frame being received. once a command/data pair is received, the zsc31010 will perform that command. after the command has been successfully executed by the ic, the ic w ill acknowledge success by a transmission of an a5 h - byte back to the master. if the master does not receive an a5 h transmission within 130 ms of issuing the command, it must assume the command was either improperly received or could not be executed. figur e 3 . 4 read acknowledge the zsc31010 transmits 10 - bit bytes (1 start bit, 8 data bits, 1 parity bit). during calibration and configuration, transmissions are normally either a5 h or data. a5 h indicates succes sful completion of a command. there are two different digital output modes configurable (digital output with temperature, and digital output with only bridge data). during normal operation mode, if the part is configured for digital output of the bridge re ading, it first transmits the high byte of bridge data, followed by the low byte. the bridge data is 14 bits in resolution, so the upper two bits of the high byte are always zero - padded. there is a 32 s stop time when the bus is held high between bytes in a packet. figure 3 . 5 digital output (nom) bridge readings 2 data byte packet (dig ital bridge output ) p 7 6 5 4 3 2 1 0 stop s p 0 0 5 4 3 2 1 0 s data byte bridge high data byte bridge low s p 2 stop start bit parity bit of data byte data bit (example: bit 2) 32 s
zsc31010 datasheet ? 2016 integrated device technology, inc. 22 january 20, 2016 the second digital output mode is digital output bridge reading with temperature. it will be transmitted as a 3 - data - byte packet. the temperature byte represents an 8 - bit temperature quantity, spanning from - 50 to 150c. figure 3 . 6 digital output (nom) bridge readings wit h temperature the eeprom transmission occurs in a packet with 14 data bytes, as shown below. figure 3 . 7 read eeprom contents there is a variable idl e time between packets, which varies with the update rate setting in the eeprom. figure 3 . 8 transmission of a number of data packets s p p st o p s p s p s idle t ime 0 0 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 5 4 idle time idle time 1 0 p st o p s 2 packet transmission (this example shows 2 data packets) 14 data byte packet (read eeprom ) p 7 6 5 4 3 2 1 0 p stop s 3 stop s p s stop s p 7 6 5 4 3 2 1 0 7 6 5 4 5 4 3 2 1 0 1 0 1 0 0 1 0 1 ... eeprom byte 13 data byte a5 h eeprom byte 12 eeprom byte 2 eeprom byte 1 3 data byte packet (digital bridge output with temperature ) p 7 6 5 4 3 2 1 0 stop s p 0 0 5 4 3 2 1 0 s data byte bridge high data byte bridge low p 7 6 5 4 3 2 1 0 stop s data byte temperature
zsc31010 datasheet ? 2016 integrated device technology, inc. 23 january 20, 2016 zacwire tm output calculation 160 ms settling time 64 ms power-on settling 128 ms power down (determined by update rate) adc conversion 768 ms calculation 160 ms zacwire tm output tabl e 3 . 2 shows the idle time between packets versus the update rate. this idle time can vary by nominal +/ - 15% between parts, and over a temperature range of - 50 to 150 o c. transmissions from the ic occur at one of two speeds depending on the update rate prog rammed in eeprom. if the user chooses one of the two fastest update rates (1 ms or 5 ms) then the baud rate of the digital transmis sion will be 32 khz (minimum 25 khz). if, however, the user chooses one of the two slower update rates (25 ms or 125 ms), th en the baud rate of the digital transmission will be 8 khz (maximum 9.4 khz). the total transmission time for both digital output configurations is shown in table 3 . 2 . table 3 . 2 total transmission time for different update rate settings and output configuration update rate baud rate * idle time transmission time ? bridge only readings transmission time ? bridge & temperature readings 1 ms (1 khz) 32 khz 1.0 ms 20.5 bi ts 31.30 s 1.64 ms 31.0 bits 31.30 s 1.97 ms 5 ms (200 hz) 32 khz 4.85 ms 20.5 bits 31.30 s 5.49 ms 31.0 bits 31.30 s 5.82 ms 25 ms (40 hz) 8 khz 22.5 ms 20.5 bits 125.00 s 25.06 ms 31.0 bits 125.00 s 26.38 ms 125 ms (8 hz) 8 khz 118.0 ms 20.5 bit s 125.00 s 120.56 ms 31.0 bits 125.00 s 121.88 ms * typical values. minimum baud rate for 1 ms or 5 ms: 26khz; maximum baud rate for 25 ms or 125 ms: 9.4khz. the temperature raw reading is performed less often than a bridge reading, because the temper ature changes more slowly. table 3 . 3 shows the timing for the special measurements (temperature and bridge measurement) in the different update rate modes. table 3 . 3 s pecial measurement versus update rate update rate setting special measurement 00 every 128 bridge measurements 01 every 64 bridge measurements 10 every 16 bridge measurements 11 every 8 bridge measurements it is easy to program any standard microcon troller to communicate with the zsc31010 . idt can provide sample code for a microchip ? pic microcontroller. for update rates less than 1 khz, the output is followed by a power - down, as shown below. figure 3 . 9 zacwire? output timing for lower update rates
zsc31010 datasheet ? 2016 integrated device technology, inc. 24 january 20, 2016 3.2.5. high level protocol the zsc31010 will listen for a command/data pair to be transmitted for the 6 ms after the de - assertion of its internal power - on reset (por). if a transmission is not received within this time frame, then it will transition to normal operation mode (nom). in nom, it will output bridge data in 0 to 1 v analog, rail - to - rail ratiometric analog output, or digital output, depending on how the part is currently configured. if the zsc31010 re ceives a start cm command within the first 6 ms after the de - assertion of por, then it will go into command mode (cm). in this mode, calibration/configuration commands will be executed. the zsc31010 will acknowledge successful execution of commands by tran smission of an a5 h . the calibrating/ configuring master will know that a command was not successfully executed if no response is received after 130 ms of issuing the command. once in command interpreting/executing mode, the zsc31010 will stay in this mode until power is removed, or a start nom (start normal operation mode) command is received. the start cm command is used as an interlock mechanism, to prevent a spurious entry into command mode on power - up. the first command received within the 6 ms window o f por must be a start cm command to enter into command interpreting mode. any other commands will be ignored. 3.3. command/data bytes encoding the 16 - bit command/data stream sent to the zsc31010 can be broken into 2 bytes, shown in table 3 . 4 . the most significant byte encodes the command byte. the least significant byte represents the data byte. table 3 . 4 command/data bytes encoding command byte data byte description 00 h xx h read eeprom command via sig ? pin; for more details, refer to section 3.7 . 20 h 5x h enter test mode (subset of command mode for test purposes only): sig? pin will assume the value of different internal test poi nts depending on the most significant nibble of data sent. dac ramp test mode. gain_b[13:3] contains the starting point, and the increment is (offset_b/8). the increment will be added every 125 sec. 30 h dd h trim/configure: higher nibble of data byte dete rmines what is trimmed/configured. lower nibble is data to be programmed. see table 3 . 5 for configuration details of data byte dd h . 40h 00 h start nom => ends command mode, transition to normal operation mode 10 h start raw mode (rm) in this mode, if gain_b = 800 h and gain_t = 80 h , then the digital output will simply be the raw values of the adc for the bridge reading and the ptat conversion. 50 h xx h start_cm => start the command mode; used to enter command interp ret mode 60 h dd h program sot (2 nd order term) 70 h dd h program t setl 80 h dd h program gain_b, upper 7 bits (set msb of dd h to 0 b ) 90 h dd h program gain_b, lower 8 bits a0 h dd h program offset_b, upper 6 bits (set the two msbs of dd h to 00 b ) b0 h dd h progr am offset_b, lower 8 bits c0 h dd h program gain_t d0 h dd h program offset_t
zsc31010 datasheet ? 2016 integrated device technology, inc. 25 january 20, 2016 command byte data byte description e0 h dd h program tco f0 h dd h program tcg table 3 . 5 programming details for command 30 h 3 rd nibble 4 th nibble description 0 h xbbb b trim oscillator; only least significant 3 bits of data used ( xbbb b ). 1 h bbbb b trim 1 v reference; least significant 4 bits of data used ( bbbb b ). 2 h xxbb b offset mode; only least significant 2 bits of data used ( xxbb b ). 3 h xxbb b set output mode; only lea st significant 2 bits of data used ( xxbb b ). 4 h xxbb b set update rate; only least significant 2 bits of data used ( xxbb b ). 5 h bbbb b configure jfet regulation 6 h bbbb b program the tc_cfg register. 7 h bbbb b program bits [99:96] of eeprom. (sot_cfg, pamp_g ain) 3.4. calibration sequence although the zsc31010 can function with many different types of resistive bridges, assume it is connected to a pressure bridge for the following calibration example. in this case, calibration essentially involves collecting raw bridge and temperature data from the zsc31010 for different known pressures and temperatures. this raw data can then be processed by the calibration master (the pc), and the calculated coefficients can then be written to the eeprom of the zsc31010 . idt can provide software and hardware with samples to perform the calibration. there are three main steps to calibration: 1. assigning a unique identification to the zsc31010 . this identification is programmed into the eeprom and can be used as an index into the database stored on the calibration pc. this database will contain all the raw values of bridge readings and temperature reading for that part, as well as the known pressure and temperature the bridge was exposed to. this unique identification can be store d in a combination of the following eeprom registers: t setl , tcg, tco. these registers will be overwritten at the end of the calibration process, so this unique identification is not a permanent serial number. 2. data collection. data collection involves gett ing raw data from the bridge at different known pressures and temperatures. this data is then stored on the calibration pc using the unique identification of the ic as the index to the database. 3. coefficient calculation and write. once enough data points ha ve been collected to calculate all the desired coefficients, then the coefficients can be calculated by the calibrating pc and written to the ic.
zsc31010 datasheet ? 2016 integrated device technology, inc. 26 january 20, 2016 step 1: assigning unique identification assigning a unique identification number is as simple as using the com mands program t setl , program tcg, and program tco. these three 8 - bit registers will allow for 16m unique devices. in addition, gain_b must be programmed to 800 h (unity), and gain_t must be programmed to 80 h (unity). step 2: data collection the number of di fferent unique (pressure, temperature) points that calibration needs to be performed at depends on the customer?s needs. the minimum is a 2 - point calibration, and the maximum is a 5 - point calibration. to acquire raw data from the part, instruct the zsc3101 0 to enter raw mode. this is done by issuing a start_cm (start command mode, 5000 h ) command to the ic, followed by a start_rm (start raw mode, 4010 h ) command with the lsb of the upper data nibble set. now, if the gain_b term was set to unity (800 h ) and the gain_t term was also set to unity (80 h ), then the part will be in raw mode and will be outputting raw data on its sig? pin, instead of corrected bridge and temperature values. the calibration system should now collect several of these data points (16 each of bridge and temperature is recommended) and average them. these raw bridge and temperature measurements should be stored in the database, along with the known pressure and temperature. the output format during raw mode is bridge_high, bridge_low, temp, each of these being 8 - bit quantities. the upper 2 bits of bridge_high are zero - filled. the temp data (8 - bit only) would not really be enough data for accu - rate temperature calibration. therefore, the upper 3 bits of temperature information are not given, b ut rather assumed known. th erefore , effectively 11 bits of temperature information are provided in this mode. step 3: coefficient calculations the mathematical equation s used to perform the coefficient calculation are quite complicated; therefore only a ba sic overview is provided in section 3.6 . idt will, however, provide software to perform the coefficient calcu - lation and the source code algorithms in a c - code format upon request. once the coefficients are calculated, the final step is to write them to the eeprom of the zsc31010 . the number of calibration points required can be as few as two or as many as five. this depends on the precision desired, and the behavior of the resistive bridge in use. ? 2 - point ca libration would be used to obtain only a gain and offset term for bridge compensation with no temperature compensation for either term. ? 3 - point calibration would be used to also obtain the tco term for 1 st order temperature compensation of the bridge offse t term. ? 3 - point calibration could also be used to obtain the additional term sot for 2 nd order correction for the bridge (sot_br), but no temperature compensation of the bridge output; see section 3.6.2.7 for li mitations. ? 4 - point calibration would be used to also obtain both, the tco term and the tcg term, which provides 1 st order temperature compensation of the bridge offset gain term. ? 4 - point calibration could also be used to obtain the tco term and the sot_br term; see section 3.6.2.7 for limitations. ? 5 - point calibration would be used to obtain tco, tcg, and an sot term that provides 2 nd order correction applied to one and only one of the following: 2 nd order tco (so t_tco), 2 nd order tcg (sot_tcg), or 2 nd order bridge (sot_br); see section 3.6.2.7 for limitations.
zsc31010 datasheet ? 2016 integrated device technology, inc. 27 january 20, 2016 3.5. eeprom bits table 3 . 6 shows the bit order in the eeprom, which are pr ogrammed through the serial interface. see table 5 . 1 for the zsc31010 default settings. table 3 . 6 zsc31010 eeprom bits eeprom range description notes 2:0 osc_trim see the table in section 2.5.1 for complete data. 100 => fastest 101 => 3 clicks faster than nominal 110 => 2 clicks faster than nominal 111 => 1 click faster than nominal 000 => nominal 001 => 1 click slower than nominal 010 => 2 clicks slower than nominal 011 => slowest 6:3 1v_trim/jfet_trim see the table in section 2.4.3 . 8:7 a2d_offset offset selection: 11 => [ - 1/2,1/2] mode bridge inputs 10 => [ - 1/4,3/4] mode brid ge inputs 01 => [ - 1/8,7/8] mode bridge inputs 00 => [ - 1/16,15/16] mode bridge inputs to change the bridge signal polarity, set tc_cfg[3](=bit 87). 10:9 output_select 00 => digital (3 - bytes with parity): bridge high {00,[5:0]} bridge low [7:0] temp [7:0 ] 01 => 0 - 1 v analog 10 => rail - to - rail ratiometric analog output 11 => digital (2 - bytes with parity) (no temp) bridge high {00,[5:0]} bridge low [7:0] 12:11 update_rate 00 => 1 msec (1 khz) 01 => 5 msec (200 hz) 10 => 25 msec (40 hz) 11 => 125 msec (8 h z) 14:13 jfet_cfg 00 => no jfet regulation (lower power) 01 => no jfet regulation (lower power) 10 => jfet regulation centered around 5.0 v 11 => jfet regulation centered around 5.5 v (i.e. over - voltage protection).
zsc31010 datasheet ? 2016 integrated device technology, inc. 28 january 20, 2016 eeprom range description notes 29:15 gain_b bridge gain: gain_b[14] = > multiply x 8 gain_b[13:0] => 14 - bit unsigned number representing a number in the range [0,8) 43:30 offset_b signed 14 - bit offset for bridge correction 51:44 gain_t temperature gain coefficient used to correct ptat reading. 59:52 offset_t temperature offset coefficient used to correct ptat reading. 67:60 t setl raw ptat reference value. (see technical note ? zsc31010, zsc31015, and zssc3015 calibration sequence, dll, and exe for details. ) 75:68 tcg coefficient for temperature correction of bridge gain term. tcg = 8 - bit magnitude of tcg term. sign is determined by tc_cfg (bits 87:84). 83:76 tco coefficient for temperature correction of bridge offset term. tco = 8 - bit magnitude of tco term. sign and scaling are determined by tc_cfg (bits 87:84). 87:8 4 tc_cfg this 4 - bit term determines options for temperature compensation of the bridge: tc_cfg[3] => if set, bridge signal polarity flips. tc_cfg[2] => if set, tcg is negative. tc_cfg[1] => scale magnitude of tco term by 8, and if sot applies to tco, scal e sot by 8. tc_cfg[0] => if set, tco is negative. 95:88 sot 2 nd order term. this term is a 7 - bit magnitude with sign. sot[7] = 1 ? negative sot[7] = 0 ? positive sot[6:0] = magnitude [0 - 127] this term can apply to a 2 nd order tcg, tco or bridge correction * . (see tc_cfg above.) * the sot range for the bridge correction is limited for the negative value to 0xc0 by the mathlib.dll . see technical note ? zsc31010, zsc31015, and zssc301 5 calibration sequence, dll, and exe for details.
zsc31010 datasheet ? 2016 integrated device technology, inc. 29 january 20, 2016 eeprom range description notes 99:96 {sot_cfg, pamp_gain} bits [99:98] = sot_cfg (for more details, see section 3.6.1 .) 00 = sot applies to bridge 01 = sot applies to tcg 10 = sot applies to tco 11 = prohibited bit s [97:96] = preamp gain 00 => 6 01 => 24 (default setting) 10 => 12 11 => 48 (only the default gain setting (24) is tested at the factory; all other gain settings are not guaranteed.) 3.6. calibration math 3.6.1. correction coefficients all terms are calculated ext ernal to the ic and then programmed to the eeprom through the serial interface. table 3 . 7 correction coefficients coefficient description gain_b gain term used to compensate span of bridge reading offset_b o ffset term used to compensate offset of bridge reading gain_t gain term used to compensate span of temp reading offset_t offset term used to compensate offset of temp reading sot second order term. the sot can be applied as a second order correction ter m for the following: - bridge measurement - temperature coefficient of offset (tco) - temperature coefficient of gain (tcg) the eeprom bits 99:98 determine what sot applies to. note: there are limitations for the sot for the bridge measurement and for the sot fo r the tco, which are explained in section 3.6.2.7 . t setl raw ptat reference value. ( see technical note ? zsc31010, zsc31015, and zssc3015 calibration sequence, dll, and exe for details . ) tcg temperature correcti on coefficient of bridge gain term (this term has an 8 - bit magnitude and a sign bit (tc_cfg[2]). tco temperature correction coefficient of bridge offset term (this term has an 8 - bit magnitude, a sign bit (tc_cfg[0]), and a scaling bit (tc_cfg[1]), which c an multiply its magnitude by 8).
zsc31010 datasheet ? 2016 integrated device technology, inc. 30 january 20, 2016 3.6.2. interpretation of binary numbers for correction coefficients br_raw should be interpreted as an unsigned number in the set [0, 16383] with a resolution of 1. t_raw should be interpreted as an unsigned number in the set [0, 16383], with a resolution of 4. 3.6.2.1. gain_b interpretation gain_b should be interpreted as a number in the set [0, 64]. the msb (bit 14) is a scaling bit that will multi ply the effect of the remaining bits gain_b[13:0] by 8. bits gain_b[13:0] represent a numb er in the range of [0, 8], with gain_b[13] having a weighting of 4, and each subsequent bit has a weighting of ? the previous bit. table 3 . 8 gain_b[13:0] weightings bit position weighting 13 2 2 = 4 12 2 1 = 2 11 2 0 = 1 10 2 - 1 ... ... 3 2 - 8 2 2 - 9 1 2 - 10 0 2 - 11 examples: the binary number: 010010100110001 b = 4.6489; gain_b[14] is 0 b , so the number represented by gain_b[13:0] is not multiplied by 8. the binary number: 101100010010110 b = 24.586; gain_b[14] is 1 b , so the number represented by gain_b[13:0] is multiplied by 8. limitation: using the 5 - point calibration 5pt - tcg&tco&sot_tco (including the second order sot_tco), the gain_b is limited to a value equal or less than 8 (instead of 64).
zsc31010 datasheet ? 2016 integrated device technology, inc. 31 january 20, 2016 3.6.2.2. offset_b interp retation offset_b is a 14 - bit signed binary number in two?s complement form. the msb has a weighting of - 8192. the following bits then have a weighting of 4096, 2048, 1024, ? table 3 . 9 offset_b weightings bit position weighting 13 -8192 12 2 12 = 4096 11 2 11 = 2048 10 2 10 = 1024 ... ... 3 2 3 = 8 2 2 2 = 4 1 2 1 = 2 0 2 0 = 1 for example, the binary number 11111111111100 b = - 4 3.6.2.3. gain_t interpretation gain_t should be interpreted as a number in the set [0,2]. gain_t[7] has a weighting of 1, and each sub sequent bit has a weighting of ? the previous bit. table 3 . 10 gain_t weightings bit position weighting 7 2 0 = 1 6 2 - 1 5 2 - 2 4 2 - 3 3 2 - 4 2 2 - 5 1 2 - 6 0 2 - 7
zsc31010 datasheet ? 2016 integrated device technology, inc. 32 january 20, 2016 3.6.2.4. o ffset_t interpretation offset_t is an 8 - bit signed binary number in two?s complement form. the msb has a weighting of - 128. the following bits then have a weighting of 64, 32, 16 ? table 3 . 11 offset_t weightin gs bit position weighting 7 -128 6 2 6 = 64 5 2 5 = 32 4 2 4 = 16 3 2 3 = 8 2 2 2 = 4 1 2 1 = 2 0 2 0 = 1 for example, the binary number 00101001 b = 41. 3.6.2.5. tco interpretation tco is specified as an 8 - bit magnitude with an additional sign bit (tc_cfg[0]), and a scalar bit (tc_cfg[1]). when the scalar bit is set, the signed tco is multiplied by 8. tco resolution: 0.175 v/v/ o c (input referred) tco range: 44.6 v/v/ o c (input referred) if the scaling bit is used, then the above resolution and range are scal ed by 8 to give the following results: tco scaled resolution: 1.40 v/v/ o c (input referred) tco scaled range: 357 v/v/ o c (input referred) 3.6.2.6. tcg interpretation tcg is specified as an 8 - bit magnitude with an additional sign bit (tc_cfg[2]). tcg resolution: 17.0 ppm/ o c tcg range: 4335 ppm/ o c
zsc31010 datasheet ? 2016 integrated device technology, inc. 33 january 20, 2016 3.6.2.7. sot interpretation sot is a 2 nd order term that can apply to one and only one of the following: bridge non - linearity correction, tco non- linearity correction, or tcg non - linearity correction. as it applies to bridge non - linearity correction: resolution: 0.25% @ full scale 2 nd order correction sot_br is possible up to +5%/ - 6.2% full scale difference from the ideal fit (straight line), because the sot coefficient values are limited to the range of (0xc0 = - 0.25 dec ) to (0x7 f = 0.4960938 dec ). (saturation in internal arithmetic will occur at greater negative non - linearities.) limitation: using any calibration method for which sot is applied to the bridge measurement (sot_br), there is a possibility of calibration math overflow . this only occurs if the sensor input exceeds 200% of the calibrated full span, which means the highest applied sensor input should never go higher than this value. example : this example of the limitation when sot is applied to the bridge reading uses a p ressure sensor bridge that outputs - 10 mv at the lowest pressure of interest. that point is calibrated to read 0%. the same sensor outputs +40 mv at the highest pressure of interest. that point is calibrated to read 100%. this sensor has a 50 mv span over the pressure range of interest. if the sensor were to experience an over - pressure event that took the sensor output up to 90 mv (200% of span), the internal calculations could overflow. the result would be a corrected bridge reading that would not be satur ated at 100% as expected, but instead read a value lower than 100%. this problem only occurs when sot is applied to correct the bridge reading. as sot applies to tcg: resolution: 0.3 ppm/( o c) 2 range: 38 ppm/( o c) 2 as it applies to tco: two settings are po ssible. it is possible to scale the effect of sot by 8. if tc_cfg[1] is set, then both, tco and sot?s contribution to tco, are multiplied by 8. resolution at unity scaling: 1.51 nv/v/( o c) 2 (input referred) range: 0.192 m v/v/( o c) 2 (input referred) resolution at 8x scaling: 12.1 nv/v/( o c) 2 (input referred) range: 1.54 m v/v/( o c) 2 (input referred) limitation: if the second order term sot applies to tco, the bridge gain gain_b is limited to values equal or less than 8 (inste ad of 64).
zsc31010 datasheet ? 2016 integrated device technology, inc. 34 january 20, 2016 3.7. reading eeprom contents the contents of the entire eeprom memory can be read using the read eeprom command (00 h ). this command causes the ic to output consecutive by t es on the zacwire?. after each transmission, the eeprom contents are shifted by 8 bits. the bit order of these bytes is given in table 3 . 12 . table 3 . 12 eeprom read order bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 1 offset_b[ 7:0] byte 2 gain_t[1:0] offset_b[13:8] byte 3 offset_t[1:0] gain_t[7:2] byte 4 t setl [1:0] offset_t[7:2] byte 5 tcg[1:0] t setl [7:2] byte 6 tco[1:0] tcg[7:2] byte 7 tc_cfg[1:0] tco[7:2] byte 8 sot[5:0] tc_cfg[3:2] byte 9 osc_trim[1:0] sot_cfg[3:0] * sot[7:6] byte 10 output_ select[0] a2d_offset[1:0] 1v_trim[3:0] ** osc_trim[2] byte 11 gain_b[2:0] jfet_cfg[1:0] update_rate[1:0] output_ select[1] byte 12 gain_b[10:3] byte 13 offset_b[3:0] *** gain_b[14:11] byte 14 a5 h * sot_cfg/pamp_gain ** 1v_trim/jfet_trim *** duplicates first 4 bits of byte 1
zsc31010 datasheet ? 2016 integrated device technology, inc. 35 january 20, 2016 4 application circuit examples note: the typical output analog load res istor r l = 10 k ? (minimum 2.5 k ? ). this optional load resistor can be configured as a pull - up or pull - down. if it is configured as a pull - down, it cannot be part of the module to be calibrated because this would prevent proper operation of the zacwire?. if a pull - down load is desired, it must be added to the system after module calibration. there is no output load capacitance needed. eeprom contents: output_select, jfet_cfg, 1v_trim/jfet - trim 4.1. three - wire rail - to - rail ratiometric output this example shows an application circuit for rail - to - rail ratiometric voltage output configuration with temperature compensation via internal ptat. the same circuitry is applicable for a 0 to 1 v absolute analog output. figure 4 . 1 rail - to - rail ratiometric voltage output 2 1 5 6 7 8 3 4 zsc31010 bsink vbp n/c vbn vss sig tm vdd vgate 0.1 mf v supply ground +2.7 to +5.5 v out optional bsink 10 nf the optional bridge sink allows power savings switching off the bridge current. the output voltage can be one of the following options: ? rail - to - rail ratiometric analog output v dd (= v s upply ). ? 0 to 1 v absolute analog output. the absolute voltage output reference is trimmable 1 v ( 3 mv) in the 1 v output mode via a 4 - bit eeprom field (see section 2.4.3 ).
zsc31010 datasheet ? 2016 integrated device technology, inc. 36 january 20, 2016 4.2. absolute analog voltage output the fig ure below shows an application circuit for an absolute voltage output configuration with temperature compensation via internal temperature ptat, and external jfet regulation for all industry standard applications. the gate - source cutoff voltage (v gs ) of th e selected jfet must be - 2 v. figure 4 . 2 absolute analog voltage output 2 1 5 6 7 8 3 4 zsc 31010 bsink vbp n / c vbn vss s ig tm vdd vgate 0 . 1 m f v supply ground + 5 . 5 to + 30 v out optional bsink s d mmbf 4392 10 n f the output signal range can be one of the following options: ? 0 to 1 v analog output. the absolute voltag e output reference is trimmable: 1 v ( 3 mv) in the 1 v output mode via a 4 - bit eeprom field (see section 2.4.3 ). ? rail - to - rail analog output. the on - chip reference for the jfet regulator block is trimmable: 5 v ( 1 5 mv) in the ratiometric output mode via a 4 - bit eeprom field (see section 2.4.3 ). 4.3. three - wire ratiometric output with over - voltage protection the figure below shows an application circuit for a ratiometric output configuration with temperature compensation via an internal diode. in this application, the jfet is used for over - voltage protection. jfet_cfg bits [14:13] in eeprom are configured to 5.5 v. there is an additional maximum error of 8 mv caused by the non - zero r on of the limiter jfet. figure 4 . 3 ratiometric output, temperature compensation via internal diode 2 1 5 6 7 8 3 4 zsc31010 bsink vbp n/c vbn vss sig tm vdd vgate 0.1 mf v supply ground +4.5 to +5.5 v out optional bsink s d j107 vishay 10 nf
zsc31010 datasheet ? 2016 integrated device technology, inc. 37 january 20, 2016 4.4. digital output for all three circuits, the output signal can also be digital. depending on the output select bits, the bridge signal, or the bridge signal and temperature signal are sent. for the digital output, no load resistor , or load capacity are necessary. no pull - down resistor is allowed. if a line resistor or pull - u p resistor is used, the requirement for the rise time must be met ( 5 s). the ic output includes a pull - up resistor of about 30 k ? . the digital output can easily be read by firmware from a microcontroller, and idt can provide the customer with software in developing the interface. 4.5. output short protection the output of the zsc31010 has no short protection. therefore, a resistor r sp in series with the output must be added in the application module. refer to table 4 . 1 to determine the value of rsp ? . to minimize additional error caused by this resistor for the analog output voltage, the load impedance must meet the following requirement: r l >> r sp table 4 . 1 resistor values for short protection temperature range (t ambmax ) resistor r sp note up to 85c 51 ? r sp = v dd /i max with i max = ( [(170c - t ambmax )/(163 c /w)] - v dd ? i dd ) / vdd up to125c 100 ? up to 150c 240 ? ? tested at v dd =5v for 20 minutes for t ambmax .
zsc31010 datasheet ? 2016 integrated device technology, inc. 38 january 20, 2016 5 default eeprom settings if needed, the default setting for the zsc31010 can be reprogrammed as described in section 3 . table 5 . 1 factory settings for the zsc31010 eeprom eeprom range name default values (hex) until week 9/2006 default values (hex) since week 10/2006 default values (hex) since week 48/2008 2:0 osc_trim 0xx 0xx 0xx 6:3 1v_trim/jfet_trim 0xx 0xx 0xx 8:7 a2d_offset 0x0 0x3 0x3 10:9 output_select 0x3 0x2 0x2 12:11 update_rate 0x2 0x1 0x1 14:13 jfet_cfg 0x1 0x2 0x2 29:15 gain_b 0x800 0x0 0x3fff 43:30 o ffset_b 0x0 0x203 0x00ff 51:44 gain_t 0x80 0x80 0x80 59:52 offset_t 0x0 0x0 0x0 67:60 t setl 0x0 0x0 0x0 75:68 tcg 0x0 0x0 0x0 83:76 tco 0xe 0x0 0x0 87:84 tc_cfg 0x0 0x0 0x0 95:88 sot 0x0 0x0 0x0 99:96 {sot_cfg, pamp_g ain} 0x1 0x5 0x5
zsc31010 datasheet ? 2016 integrated device technology, inc. 39 january 20, 2016 1 2 3 4 8 7 6 5 bsink vbp n/c vbn vss sig tm vdd vgate 6 pin configuration and package the standard package of the zsc31010 is an sop - 8 (3.81 mm / 150 mil body) with a lead - pitch 1.27 mm / 50 mil. table 6 . 1 storage and soldering conditions for the sop - 8 package parameter symbol conditions min typ max unit maximum storage temperature t max _ storage less than 10hrs, before mounting 150 c minimum storage temperature t min _ storage store in original packing only -5 0 c maximum dry - bake temperat ure t drybake less than100 hrs total, before mounting 125 c soldering peak temperature t peak less than 30s (ipc/jedec - std - 020 standard) 260 c figure 6 . 1 zsc31010 pin - out diagram table 6 . 2 zsc31010 pin configuration pin no. name description 1 bsink optional ground connection for bridge ground. used for power savings. 2 vbp positive bridge connection 3 n/c no connection 4 vbn negative bridge connection 5 vgate gate control for external jfet regulation/over - voltage protection 6 vdd supply voltage (2.7 - 5.5 v) 7 sig? zacwire? interface (analog out, digital out, calibration interface) 8 vss ground supply
zsc31010 datasheet ? 2016 integrated device technology, inc. 40 january 20, 2016 7 esd/latch - up - protection all pins have an esd protection of > 4000 v and a latch - up protection of 100 ma or of +8v/ - 4 v (to vss/vssa). esd protection referred to the human body model is tested with devices in sop - 8 packages during product qualification. the esd test follows the human body model with 1.5 k /100 pf based on mil 883, method 3015.7. 8 test the test program is based on this datasheet. the final parameters that will be tested during series production are listed in the tables of section 1 . the digital pa rt of the ic includes a scan path, which can be activated and con - trolled during wafer test. it guarantees failure coverage of more than 98%. further test support for testing of the analog parts on wafer level is included in the dsp. 9 quality and reliabilit y a reliability investigation according to the in - house non - automotive standard has been performed. 10 customization for high - volume applications which require an upgraded or downgraded functionality compared to the zsc31010 , idt can customize the circuit design by adding or removing certain functional blocks. idt can provide a custom solution quickly because it has a considerable library of sensor - dedicated circuitry blocks. please contact idt for further information.
zsc31010 datasheet ? 2016 integrated device technology, inc. 41 january 20, 2016 11 ordering code s sales code des cription package zsc31010 ceb zsc31010 die ? temperature range: - 50c to +150c unsawn on wafer zsc31010 cec zsc31010 die ? temperature range: - 50c to +150c sawn on wafer frame zsc31010 ceg1 zsc31010 sop8 (150 mil) ? temperature range: - 50c to +150c tube: add ? - t? to sales code ; r eel: add ? - r? zsc31010cib zsc31010 die ? temperature range: - 40c to 85c unsawn on wafer zsc31010cic zsc31010 die ? temperature range: - 40c to 85c sawn on wafer frame zsc31010cig1 zsc31010 sop8 (150 mil) ? temperature range: - 40c to 85c tube: add ? - t? to sales code reel: add ? - r? zsc31010 kit zsc31010 zacwire? ssc evaluation kit: communication board, ssc board, sensor replacement board, usb cable, 5 ic samples kit contact idt sales for support and sales of idt ?s zs c31010 mass calibration system. 12 related documents document zacwire? ssc evaluation kit documentation for zsc31010 and zsc31015 ssc kits feature sheet (includes ordering codes and prices) tec hnical note ? zsc31010, zsc31015, and zssc3015 calibration sequence, dll, and exe visit the zsc31010 product page at www.idt.com/zsc31010 or contact your nearest sales office for the latest version of these documents. 13 definitions of acronyms term description adc analog - to - digital converter afe analog front - end buf buffer cm command mode cmc calibration microcontroller dac digital -to - digital converter dnl differen tial nonlinearity dsp digital signal processor dut device under test esd electrostatic discharge
zsc31010 datasheet ? 2016 integrated device technology, inc. 42 january 20, 2016 term description fso full - scale output inl integrated nonlinearity lsb least significant bit mux multiplexer nom normal operation mode owi one - wire interface poc pow er - on clear por power - on reset level psrr power supply rejection ratio ptat proportional to absolute temperature rm raw mode sot second order term 14 document revision history revision date description 2.44 08- apr-20 10 clarification of part ordering c odes and addition of document revision history. 2.5 0 27- jul -20 10 revision of product name from zmd31010 to zsc31010 . 2.6 0 11- nov -2010 removed reference to mass calibration kit ; added footnote to short protection ; a dded special measurement information ( table 3 . 3 ): r evised s top bit definition ; a dded eeprom specifications to section 1.3 ?electrical parameters.? added table 6 . 1 ?storage and soldering conditions? to section 6 ?pin configuration and package.? corrected equation (2) . revised trim tolerances in section 2.4.3 . 2.7 0 30- mar -2011 rev ision in ?related documents? table for the name of the kit document. revision in table 6 . 1 to match the maximum temperature range in section 1.1 . updated trim tolerances in sections 4.1 and 4.2 . correction of formula in table 4 . 1 . 2.8 0 25- may -2011 revision of table 5 . 1 to add column for defaults as of 48/2008. revisions to description of t setl . 2.81 07- oct - 2011 revision to s ales contact information and product title . minor edit to ?benefits? section on page 2 2.82 06- jul - 2012 revision to sales contact information for zmd america, inc . 2.83 05- dec - 2012 revision to sales contact information for zentrum mi kroelektronik dresden ag, korea office. revision to phone numbers for usa office.
zsc31010 datasheet ? 2016 integrated device technology, inc. 43 january 20, 2016 revision date description 2.84 1 5 - aug -2 013 update for part codes on p age 3 and in section 11 . update for contact information and images for cover and headers. update for related documents section. update for specification for sensor signal span to 3mv/v to 105mv/v. clarification of eeprom programming temperature specification in table note in section 1.2 . 2.90 29- aug - 2013 revision of certification status in section 9 ? quality and reliability .? minor edits. 2.91 01- nov -2013 revision of specifications in section 1.2 for ?output load capacitance? to add minimum specification. revision of specifications in sec tion 1.2 for ?output load resistance.? added table note to s ection 1.2 regarding pull - down resistor . a dded 10nf output cap to all application figures. minor edits for clarity. 20- jan - 2016 changed to idt branding . corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com sales 1- 800- 345- 7015 or 408 - 284- 8200 fax: 408 - 284- 2775 www.idt.com/go/sales tech support www.idt.com/go/support disclaimer integrated device technology, inc. (idt) reserves the right to modify the products and/or specific ations described herein at any time, without notice, at idt's sole discretion. performance specifications and operating parameters of the described products are determined in an independent state and are not guarante ed to perform the same way when installe d in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, includin g, but not limited to, the suitability of idt's products for any particular purpose, an implied warrant y of merchantability, or non - infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey an y license under intellectual property rights of idt or any third parties. idt's products are not inte nded for use in applications involving extreme environmental conditions or in life support systems or similar devices where t he failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyon e using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the united states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . all contents of this document are copyright of integrated device technology, inc. all rights reserved.

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